MPC8280 datasheet(396/1386 Pages) FREESCALE

396 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-88

Freescale Semiconductor

•

Initialize the CTM (channel transfer mode) bit in the mode register to indicate chaining mode.

Other control parameters in the mode register can also be initialized here if necessary.

•

First clear then set the CS (channel start) bit in the mode register to start the DMA transfer.

9.13.1.3

DMA Coherency

The four DMA channels are allocated 4 cache lines (128 bytes) of buffer space in the I/O sequencer module

in addition to 16 bytes of local buffer space. Because no address snooping occurs in these internal queues,

data posted in these queues is not visible to the rest of the system while a DMA transfer is in progress. It

is the responsibility of application software to ensure the coherency of the region being transferred during

the DMA process.

Snooping of the core data cache is selectable during DMA transactions. A snoop bit is provided in the

current descriptor address register and the next descriptor address register which allows software to control

when the cache is snooped. These bits are described in Section 9.13.1.6.3, “DMA Current Descriptor

Address Registers 0–3 (DMACDARx),” and Section 9.13.1.6.7, “DMA Next Descriptor Address

Registers 0–3 (DMANDARx),” respectively.

9.13.1.4

Halt and Error Conditions

DMA transfers are halted either by clearing the CS (channel start) bit in the mode register or when

encountering an error condition. In both cases the application software can one of the following:

•

Continue the DMA transfer

•

Reconfigure the DMA for a new transfer

•

Leave the channel in the halted state

When a DMA channel is halted, its programming model is completely accessible. If the DMA is halted

due to an error condition, the TE (transfer error) bit in the status register must be cleared before the transfer

can be resumed or a new transfer initiated. Note that the TE bit is not cleared automatically by hardware.

NOTE: DMA Operation After Bus Error

After any bus error which occurs in the MPC8280 (either 60x or PCI, not

necessarily due to DMA operation), the user must reset the system to avoid

DMA malfunction.

9.13.1.5

DMA Transfer Types

The DMA controller supports all transfers between 60x memory and PCI memory: 60x-to-60x,

PCI-to-PCI, 60x-to-PCI, and PCI-to-60x. All data is temporarily stored in a 144-byte queue prior to

transmission. There are four types of DMA transfers:

•

PCI-memory-to-PCI-memory transfers—The DMA controller begins by reading data from PCI

memory space and storing it in the DMA queue. Once sufficient data is stored in the queue, the

DMA controller begins writing data from the queue to PCI memory space beginning at the

destination address. The process is repeated until there is no more data to transfer or an error

condition has occurred on the PCI bus.

MPC8280 Datasheet(PDF) 396 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 396 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL