MPC8280 datasheet(474/1386 Pages) FREESCALE

474 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-54

Freescale Semiconductor

11.5.1.1

Chip-Select Assertion Timing

From 0 to 30 wait states can be programmed for PSDVAL generation. Byte-write enable signals (WE) are

available for each byte written to memory. Also, the output enable signal (OE) is provided to eliminate

external glue logic. The memory banks selected to work with the GPCM have unique features. On system

reset, a global (boot) chip-select is available that provides a boot ROM chip-select prior to the system

being fully configured. The banks selected to work with the GPCM support an option to output the CS line

at different timings with respect to the external address bus. CS can be output in any of three

configurations:

•

Simultaneous with the external address

•

One quarter of a clock cycle later

•

One half of a clock cycle later

Note the GPCM does not negate CS in back-to-back reads to the same device when in single MPC8280

bus mode or in 60x-compatible bus mode with extended transfers enabled. When in strict 60x bus mode,

however, the GPCM does negate CS in back-to-back reads. See Section 4.3.2.1, “Bus Configuration

Figure 11-41 shows a basic connection between the MPC8280 and an external peripheral device. Here, CS

(the strobe output for the memory access) is connected directly to CE of the memory device and BCTL0

is connected to the respective R/W in the peripheral device.

Figure 11-41. GPCM Peripheral Device Interface

Figure 11-42 shows CS as defined by the setup time required between the address lines and CE. The user

can configure ORx[ACS] to specify CS to meet this requirement.

Address

R/W

Data

Peripheral

Data

BCTL0

Address

MPC8280

MPC8280 Datasheet(PDF) 474 Page - Freescale Semiconductor, Inc