MPC8280 datasheet(471/1386 Pages) FREESCALE

471 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-51

Now, from the SDRAM device point of view, during an ACTIVATE command, its address port should look

like Table 11-27.

Table 11-20. indicates that in order to multiplex A[6–19] over A[15–28] PSDMR[SDAM] must be 001

and, because the internal bank selects are multiplexed over A[15–16] PSDMR[BSMA] must be 010 (only

the lower two bank select lines are used).

During a READ/WRITE command, the address port should look like Table 11-28.

Because AP alternates with A[9] of the row lines, set PSDMR[SDA10] = 011. This outputs A[9] on the

SDA10 line during the ACTIVATE command and AP during READ/WRITE and CBR commands.

Table 11-29. shows the register configuration. Not shown are PSRT and MPTPR, which should be

programmed according to the device refresh requirements.

Table 11-27. SDRAM Device Address Port During ACTIVATE Command

A[0–14]

A[15–16]

A[17–28]

A[29–31]

—

Internal bank select (A[6–7])

Row (A[8–19])

n.c.

Table 11-28. SDRAM Device Address Port During READ/WRITE Command

A[0–14]

A[15–16]

A[17]

A[18]

A[19]

A[20–28]

A[29–31]

—

Internal bank select

Don’t care

Column

n.c.

Table 11-29. Register Settings (Bank-Based Interleaving)

Settings

BA Base address

PS00 = 64-bit port size

DECC00

WP0

MS010 = SDRAM-60x bus

EMEMC0

ATOM00

DR0

SDAM 1111_1100_0000

LSDAM 00000

BPD 01

ROWST 010

NUMR 011

PMSEL 0

IBID 0

PSDMR

PBI 0

RFEN 1

OP 000

SDAM 001

BSMA 010

SDA10 011

RFRC from device data sheet

PRETOACT from device data sheet

ACTTOROW from device data sheet

BL 0

LDOTOPRE from device data sheet

WRC from device data sheet

EAMUX 0

BUFCMD 0

CL from device data sheet

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