MPC8280 datasheet(472/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-52

Freescale Semiconductor

11.5

General-Purpose Chip-Select Machine (GPCM)

Users familiar with the MPC8xx memory controller should read Section 11.5.4, “Differences Between the

MPC8xx GPCM and MPC82xx GPCM,” first.

The GPCM allows a glueless and flexible interface between the MPC8280, SRAM, EPROM, FEPROM,

ROM devices, and external peripherals. The GPCM contains two basic configuration register

groups—BRx and ORx.

Although GPCM does not support bursting, the internal logic will split a burst into individual beats that

the GPCM can support. Therefore, the flash can be cached. Note that if the MPC8280 is in 60x-bus

compatible mode, BADDR[27–31] should be used instead of A[27–31].

Table 11-30 lists the GPCM interface signals on the 60x and local bus.

GPCM-controlled devices can use BCTLx as read/write indicators. The BCTLx signals appears as R/W in

the timing diagrams. See Section 11.2.7, “Data Buffer Controls (BCTLx and LWR).”

Additional control is available in 60x-compatible mode (60x bus only)—ALE–external address latch

enable

In this section, the output-enable and write-enable signals are generically labeled OE and WE. When using

the 60x bus they refer to POE and PWE, and for the local bus they refer to LOE and LWE.

Figure 11-40 shows a simple connection between a 32-bit port size SRAM device and the MPC8280.

Figure 11-40. GPCM-to-SRAM Configuration

Table 11-30. GPCM Interfaces Signals

60x Bus

Local Bus

Comments

CS[0–11]

Device select

PWE[0–7]

LWE[0–3]

Write enables for write cycles

POE

LOE

Output enable for read cycles

WE[0–3]

Address

Data

32-Bit Wide SRAM

D[0–31]

A[15–29]

GPL_x1/OE

WE[0–3]

CSx

128K

MPC8280

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