MPC8280 datasheet(611/1386 Pages) FREESCALE

611 / 1386 page

Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

15-33

When the receive and transmit section uses the same clock and sync signals, these sections should be

programmed to the same configuration. Also, the L1TXDx pin in the I/O register should be programmed

to be an open-drain output. To support the monitor and the C/I channels in GCI, those channels should be

routed to one of the SMCs. To support the D channel when there is no possibility of collision, the user

should clear the SIxMR[GRx] bit corresponding to the SCC that supports the D channel.

15.7.2.2

SCIT Programming

For interfacing the GCI/SCIT bus, SIxMR must be programmed to the GCI/SCIT mode. The SIx RAM is

programmed to support a 96-bit frame length and the frame sync is programmed to the GCI sync pulse.

Generally, the SCIT bus supports the D channel access collision mechanism. For this purpose, the user

should program the CRTx bits so the receive and transmit sections use the same clock and sync signals and

program the GRx bits to transfer the D channel grant to the SCC that supports this channel. The received

(grant) bit should be marked by programming the channel select bits of the SIx RAM to 0b0111 for an

internal assertion of a strobe on this bit. This bit is sampled by the SI and transferred to the D-channel SCC

as the grant. The bit is generally bit 4 of the C/I in channel 2 of the GCI, but any other bit can be selected

using the SIx RAM.

For example, assuming that SCC1 is connected to the D channel, SCC2 to the B1 channel, and SMC2 to

the B2 channel, SMC1 is used to handle the C/I channels, and the D-channel grant is on bit 4 of the C/I on

SCIT channel 2, the initialization sequence is as follows:

1. Program both the Tx and Rx sections of the SIx RAM as in Table 15-12 beginning at addresses 0

and 1024, respectively.

2. SI1AMR = 0x00c0. TDMa is used in double speed clock and common Rx/Tx modes. SCIT mode

is used in this example.

NOTE

If SCIT mode is not used, delete the last three entries of the SIx RAM, divide

one entry into two and set the LST bit in the new last entry.

3. CMXSMR = 0x88. SMC1 and SMC2 are connected to the TSA.

Table 15-12. SI

x RAM Entries for a GCI Interface (SCIT Mode)

Entry

Number

x RAM Entry

MCC

SWTR

SSEL

CSEL

CNT

BYT

LST

Description

0000

0010

000

8 Bits SCC2

0000

0110

000

8 Bits SMC2

0000

0101

000

8 Bits SMC1

0000

0001

001

2 Bits SCC1

0000

0101

101

6 Bits SMC1

0000

110

Skip 7 bytes

0000

001

Skip 2 bits

0000

0111

000

D grant bit

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