MPC8280 datasheet(610/1386 Pages) FREESCALE

610 / 1386 page

Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

15-32

Freescale Semiconductor

•

D is a 16-Kbps signaling channel

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C/I is a 48-Kbps C/I channel (includes A and E bits)

The M channel is used to transfer data between layer 1 devices and the control unit (the CPU); the C/I

channel is used to control activation/deactivation procedures or to switch test loops by the control unit. The

M and C/I channels of the GCI bus should be routed to SMC1 or SMC2, which have modes to support the

channel protocols. The MPC8280 can support any channel of the GCI bus in the primary rate by modifying

SIx RAM programming.

The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation since it can

access each bit of the GCI separately. The current-route RAM specifies which bits are supported by the

interface and which serial controller support them. The receiver only receives the bits that are enabled by

the SIx RAM and the transmitter only transmits the bits that are enabled by the SIx RAM and does not

drive L1TXDx. Otherwise, L1TXDx is an open-drain output and should be pulled high externally.

The MPC8280 supports contention detection on the D channel of the SCIT bus. When the MPC8280 has

data to transmit on the D channel, it checks a SCIT bus bit that is marked with a special route code (usually,

bit 4 of C/I channel 2). The physical layer device monitors the physical layer bus for activity on the D

channel and indicates on this bit that the channel is free. If a collision is detected on the D channel, the

physical layer device sets bit 4 of C/I channel 2 to logic high. The MPC8280 then aborts its transmission

and retransmits the frame when this bit is set again. This procedure is automatically handled for the first

two buffers of a frame.

15.7.1

SI GCI Activation/Deactivation Procedure

In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The layer 1 device

activates the MPC8280 by enabling the clock pulses and by an indication in the channel 0 C/I channel. The

MPC8280 reports to the core (via a maskable interrupt) that a valid indication is in the SMC RxBD.

When the core activates the line, the data output of L1TXDn is programmed to zero by setting

SIxGMR[STZx]. Code 0 (command timing TIM) is transmitted on channel 0 C/I channel to the layer 1

device until STZx is reset. The physical layer device resumes the clock pulses and gives an indication in

the channel 0 C/I channel. The core should reset STZx to enable data output.

15.7.2

Serial Interface GCI Programming

The following sections describe serial interface GCI programming.

15.7.2.1

Normal Mode GCI Programming

The user can program and configure the channels used for the GCI bus interface. First, the SIxMR register

to the GCI/SCIT mode for that channel must be programmed, using the DSCx, FEx, CEx, and RFSDx bits.

This mode defines the sync pulse to GCI sync for framing and data clock as one-half the input clock rate.

The user can program more than one channel to interface to the GCI bus. Also, if the receive and transmit

section are used for interfacing the same GCI bus, the user internally connects the receive clock and sync

signals to the SIx RAM transmit section, using the CRTx bits. The user should then define the GCI frame

routing and strobe select using the SIx RAM.

MPC8280 Datasheet(PDF) 610 Page - Freescale Semiconductor, Inc

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