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MPC8280 Datasheet(PDF) 608 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 608 Page - Freescale Semiconductor, Inc

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Serial Interface with Time-Slot Assigner
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
15-30
Freescale Semiconductor
2. CMXSI1CR = 0x00. TDMA receive clock is CLK1.
3. CMXSMR = 0x80. SMC1 is connected to the TSA.
4. CMXSCR = 0xC040_0000. SCC1 and SCC2 are connected to the TSA. SCC1 supports the grant
mechanism because it handles the D channel.
5. SI1AMR = 0x0145. TDMA grant mode is used with 1-bit frame sync delay in Tx and Rx and
common receive-transmit mode.
6. Set PPARA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa, and L1RSYNCa.
7. Set PSORA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa, and L1RSYNCa.
8. Set PDIRA[9]. Configures L1TXDa[0].
9. Set PODRA[9]. Configures L1TXDa[0] to an open-drain output.
10. Set PPARC[30,31]. Configures L1TCLKa and L1RCLKa.
11. Clear PDIRC[30,31] Configures L1TCLKa and L1RCLKa.
12. Clear PSORC[30,31]. Configures L1TCLKa and L1RCLKa.
13. Set PPARB[17]. Configures L1RQa.
14. Clear PSORB[17]. Configures L1RQa.
15. Set PDIRB[17]. Configures L1RQa.
16. Set PPARD[13]. Configures L1ST1.
17. Clear PSORD[13]. Configures L1ST1.
18. Set PDIRD[13]. Configures L1ST1.
19. SI1CMDR is not used.
20. SI1STR does not need to be read.
21. Configure the SCC1 for HDLC operation (to handle the LAPD protocol of the D channel), and
configure SCC2 and SMC1 as preferred.
22. SI1GMR = 0x01. Enable TDM A (one static TDM).
23. Enable SCC1, SCC2 and SMC1.
15.7
Serial Interface GCI Support
The MPC8280 fully supports the normal mode of the GCI, also known as the ISDN-oriented modular
revision 2.2 (IOM-2), and the SCIT. The MPC8280 also supports the D-channel access control in S/T
interface terminals using the command/indication (C/I) channel
4
0
0
0000
0101
011
0
0
4-bit SMC1
5
0
0
1000
0001
000
0
1
1-bit SCC1
strobe1
Table 15-10. SI
x RAM Entries for an IDL Interface (continued)
Entry
Number
SI
x RAM Entry
MCC
SWTR
SSEL
CSEL
CNT
BYT
LST
Description



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