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MPC8280 Datasheet(PDF) 606 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 606 Page - Freescale Semiconductor, Inc |
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606 / 1386 page ![]() Serial Interface with Time-Slot Assigner MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 15-28 Freescale Semiconductor The basic rate IDL bus has the three following channels: • B1 is a 64-Kbps bearer channel • B2 is a 64-Kbps bearer channel • D is a 16-Kbps signaling channel There are two definitions of the IDL bus frame structure—8 and 10 bits. The only difference between them is the channel order within the frame. See Figure 15-23. Figure 15-23. IDL Bus Signals NOTE Previous versions of Freescale IDL-defined bit functions called auxiliary (A) and maintenance (M) were removed from the IDL definition when it was concluded that the IDL control channel would be out-of-band. These functions were defined as a subset of the Freescale SPI format called serial control port (SCP). To implement the A and M bits as originally defined, program the TSA to access these bits and route them transparently to an SCC or SMC. Use the SPI to perform out-of-band signaling. The MPC8280 supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame can be routed to any SCC and SMC or can assert a strobe output for supporting an external device. The MPC8280 supports the request-grant method for contention detection on the D channel of the IDL basic rate and when the MPC8280 has data to transmit on the D channel, it asserts L1RQx. The physical layer device monitors the physical layer bus for activity on the D channel and indicates that the channel is free by asserting L1GRx. The MPC8280 samples the L1GRx signal when the IDL sync signal (L1RSYNCx) is asserted. If L1GRx is asserted, the MPC8280 sends the first zero of the opening flag in the first bit of the D channel. If a collision is detected on the D channel, the physical layer device negates L1GRx. The L1CLK L1SYNC L1RXD L1TXD B1 D1 10-Bit IDL D2 B1 D1 B2 D2 L1RXD L1TXD B1 D1 8-Bit IDL D2 B1 B2 D2 B2 D1 B2 Notes: 1. Clocks are not to scale. 2. L1RQ x and L1GRx are not shown. |
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