MPC8280 datasheet(609/1386 Pages) FREESCALE

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Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

15-31

The GCI bus consists of four lines—two data lines, a clock, and a frame synchronization line. Usually, an

8-kHz frame structure defines the various channels within the 256-kbps data rate. The MPC8280 supports

two (limited by the number of SMCs) independent GCI buses, each with independent receive and transmit

sections. The interface can also be used in a multiplexed frame structure on which up to eight physical

layer devices multiplex their GCI channels. In this mode, the data rate would be 2,048 kbps.

In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to produce the

data clock. The MPC8280 also has data strobe lines and the 1

× data rate clock L1CLKOx output pins.

These signals are used for interfacing devices to GCI that do not support the GCI bus. Table 15-11

describes GCI signals for each transmit and receive channel.

The GCI bus signals are shown in Figure 15-24.

Figure 15-24. GCI Bus Signals

In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and

control functions:

•

B1 is a 64-Kbps bearer channel

•

B2 is a 64-Kbps bearer channel

•

M is a 64-Kbps monitor channel

Table 15-11. GCI Signals

Signal

Description

L1RSYNC

Used as a GCI sync signal; input to the MPC8280. This signal indicates that the clock periods following

the pulse designate the GCI frame.

L1RCLK

Used as a GCI clock; input to the MPC8280. The L1RCLK

x signal frequency is twice the data clock.

L1RXD

Used as a GCI receive data; input to the MPC8280.

L1TXD

Used as a GCI transmit data; open-drain output. Valid only for the bits that are supported by the IDL;

otherwise, three-stated.

L1CLKO

Optional signal; output from the MPC8280. This 1

× clock output is used to clock devices that do not

interface directly to the GCI. If the double-speed clock is used, (DSC

x bit is set in the SIxMR), this

output is the L1RCLK

x divided by 2; otherwise, it is simply a 1

× output of the L1RCLKx signal.

Note:

x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).

L1CLK

L1SYNC

L1RXD

L1TXD

M (Monitor)

C/I

A E

M (Monitor)

C/I

A E

(2X the data rate)

Notes: Clock is not to scale.

L1CLKO is not shown.

D1 D2

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