MPC8280 datasheet(884/1386 Pages) FREESCALE

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Serial Management Controllers (SMCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

28-30

Freescale Semiconductor

15. Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This additional write

ensures that TEN and REN are enabled last.

After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is closed. Any data

received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared.

28.5

The SMC in GCI Mode

The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT configuration

of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The main features

of the SMC in GCI mode are as follows:

•

Each SMC channel supports the C/I and monitor channels of the GCI (IOM-2) in ISDN

applications

•

Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1

•

Full-duplex operation

•

Local loopback and echo capability for testing

To use the SMC GCI channels properly, the TSA must be configured to route the monitor and C/I channels

to the preferred SMC. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes how to program

this configuration. GCI mode is selected by setting SMCMR[SM] to 0b10. Section 28.2.1, “SMC Mode

Registers (SMCMR1/SMCMR2)” describes other protocol-specific SMCMR bits.

28.5.1

SMC GCI Parameter RAM

The GCI parameter RAM differs from that for UART and transparent mode. The CP accesses each SMC’s

GCI parameter table using a user-programmed pointer (SMCx_BASE) located in the parameter RAM; see

Section 14.5.2, “Parameter RAM.” Each SMC GCI parameter RAM table can be placed at any 64-byte

aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). In GCI mode,

parameter RAM contains the BDs instead of pointers to them. Compare Table 28-17 with Table 28-2 on

page 28-6 to see the differences. (In GCI mode, the SMC has no extra protocol-specific parameter RAM.)

Table 28-17. SMC GCI Parameter RAM Memory Map

Offset 1

Name

Width

Description

0x00

M_RxBD

Half

word

Monitor channel RxBD. See Section 28.5.5, “SMC GCI Monitor Channel RxBD.”

0x02

M_TxBD

Half

word

Monitor channel TxBD. See Section 28.5.6, “SMC GCI Monitor Channel TxBD.”

0x04

CI_RxBD

Half

word

C/I channel RxBD. See Section 28.5.7, “SMC GCI C/I Channel RxBD.”

0x06

CI_TxBD

Half

word

C/I channel TxBD. See Section 28.5.8, “SMC GCI C/I Channel TxBD.”

0x08

RSTATE2

Word

Rx/Tx Internal State

0x0C

M_RxD 2

Half

word

Monitor Rx Data

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