MPC8280 datasheet(885/1386 Pages) FREESCALE

885 / 1386 page

Serial Management Controllers (SMCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

28-31

28.5.2

Handling the GCI Monitor Channel

The following sections describe how the GCI monitor channel is handled.

28.5.2.1

SMC GCI Monitor Channel Transmission Process

Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers

and transferring of the S and Q bits). Monitor channel 1 is used for programming and controlling

voice/data modules such as CODECs. The core writes the byte into the TxBD. The SMC sends the data

on the monitor channel and handles the A and E control bits according to the GCI monitor channel

protocol. The TIMEOUT command resolves deadlocks when errors in the A and E bit states occur on the

data line.

28.5.2.2

SMC GCI Monitor Channel Reception Process

The SMC receives data and handles the A and E control bits according to the GCI monitor channel

protocol. When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated.

A TRANSMIT ABORT REQUEST command causes the MPC8280 to send an abort request on the E bit.

28.5.3

Handling the GCI C/I Channel

The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends commands and

receives indication to or from the upstream layer 1 device through C/I channel 0. In the SCIT

configuration, C/I channel 1 is used to convey real-time status information between the layer 2 device and

nonlayer 1 peripheral devices (CODECs).

28.5.3.1

SMC GCI C/I Channel Transmission Process

The core writes the data byte into the C/I TxBD and the SMC transmits the data continuously on the C/I

channel to the physical layer device.

0x0E

M_TxD 2

Half

word

Monitor Tx Data

0x10

CI_RxD 2

Half

word

C/I Rx Data

0x12

CI_TxD 2

Half

word

C/I Tx Data

1 From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at 0x88FC.

2 RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation, and are

reserved for RISC use only.

Table 28-17. SMC GCI Parameter RAM Memory Map (continued)

Offset 1

Name

Width

Description

MPC8280 Datasheet(PDF) 885 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 885 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL