MPC8280 datasheet(1219/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-3

•

Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt

•

May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps

are supported.

35.2

Functionality

The TC layer block is shown in Figure 35-2. The transmit and the receive parts are independent; the only

case in which they are synchronized is in cell echo mode.

Figure 35-2. TC Layer Block Diagram

35.2.1

Receive ATM Cell Functions

The ATM receive cell functions block (RCF) performs the receive functions of the TC block. It performs

cell delineation, cell payload descrambling, HEC verification and correction, and idle/unassigned cell

filtering.

Cell delineation is the process of framing data to ATM cell boundaries using the header error check (HEC)

received in the ATM cell header. The HEC is a CRC-8 calculation over the first four octets of the ATM

MPC8280

TC Layer

PHY

Rx Cell

Functions

• cell delineation

• descrambling

• coset

• HEC error

correction

Tx UTOPIA I/F

Rx UTOPIA I/F

(PHY)

Tx Serial I/F

Rx Serial I/F

Counters

Registers

FCC2

one channel

60x Bus

UTOPIA

Rx I/F

UTOPIA

Tx I/F

M-PHY

detection and

Rx FIFO

Tx FIFO

Tx Cell

Functions

• HEC generation

• scrambling

• coset

• rate adaptation

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