MPC8280 datasheet(1274/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

37-12

Freescale Semiconductor

The RxBD status bits are written by the HDLC controller after receiving the associated data buffer.

The remaining RxBD parameters are as follows:

•

Data length is the number of octets the CP writes into this BD’s data buffer. It is written by the CP

once the BD is closed. When this is the last BD in the frame (L = 1), this field contains the total

number of frame octets, including 2 or 4 bytes for CRC. The memory allocated for this buffer

should be no smaller than the MRBLR value.

•

Rx data buffer pointer. The receive buffer pointer, which always points to the first location of the

associated data buffer, resides in internal or external memory and must be divisible by 32 unless

FPSMR[TS] = 1 (see Table 37-6).

37.8

HDLC Transmit Buffer Descriptor (TxBD)

Data is presented to the HDLC controller for transmission on an FCC channel by arranging it in buffers

referenced by the channel TxBD table. The HDLC controller confirms transmission (or indicates errors)

using the BDs to inform the core that the buffers have been serviced. Figure 37-6 shows the FCC HDLC

TxBD.

Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by

eight.

Rx abort sequence. At least seven consecutive 1s are received during frame reception.

Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive

buffer.

Overrun. A receiver overrun occurs during frame reception.

Carrier detect lost. CD has negated during frame reception. This bit is valid only for NMSI mode.

0123

456

789

Offset + 0

—

—UN

Offset + 2

Data Length

Offset + 4

Tx Data Buffer Pointer

Offset + 6

Figure 37-6. FCC HDLC Transmit Buffer Descriptor (TxBD)

Table 37-7. RxBD field Descriptions (continued)

Bits

Name

Description

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