MPC8280 datasheet(1275/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

37-13

Table 37-8 describes HDLC TxBD fields.

The TxBD status bits are written by the HDLC controller after sending the associated data buffer.

The remaining TxBD parameters are as follows:

•

Data length is the number of bytes the HDLC controller should transmit from this data buffer; it is

never modified by the CP. The value of this field should be greater than zero.

•

Tx data buffer pointer. The transmit buffer pointer, which contains the address of the associated

data buffer, can be even or odd. The buffer can reside in internal or external memory. This value is

never modified by the CP.

Table 37-8. HDLC TxBD Field Descriptions

Bits

Name

Description

Ready

0 The buffer associated with this BD is not ready for transmission. The user can manipulate this BD

or its associated buffer. The CP clears R after the buffer has been sent or an error occurs.

1 The buffer is ready to be sent. The transmission may have begun, but it has not completed. The

user cannot set fields in this BD once R is set.

—

Reserved, should be cleared.

Wrap (final BD in table)

0 Not the last BD in the TxBD table.

1 Last BD in the TxBD table. After this buffer has been used, the CP sends data from the first BD

that TBASE points to in the table. The number of TxBDs in this table is determined only by the W

bit and the overall space constraints of the dual-port RAM.

Interrupt

0 No interrupt is generated after this buffer is serviced; FCCE[TXE] is unaffected.

1 Either FCCE[TXB] or FCCE[TXE] is set when this buffer is serviced by the HDLC controller.

These bits can cause interrupts if they are enabled.

Last

0 Not the last buffer in the frame.

1 Last buffer in the current frame.

Tx CRC.Valid only when the L bit is set. Otherwise, it is ignored.

0 Transmit the closing flag after the last data byte. This setting can be used to send a bad CRC after

the data for testing purposes.

1 Transmit the CRC sequence after the last data byte.

Continuous mode

0 Normal operation.

1 The R bit is not cleared by the CP after this BD is closed, allowing the buffer to be retransmitted

automatically the next time the CP accesses this BD. However, the R bit is cleared if an error

occurs during transmission, regardless of the CM bit.

7–13

—

Reserved, should be cleared.

Underrun. The HDLC controller encounters a transmitter underrun condition while sending the

buffer. The HDLC controller writes UN after sending the buffer.

CTS lost. Set when CTS is lost during frame transmission in NMSI mode. If data from more than

one buffer is in the FIFO buffer when this error occurs, CT is set in the currently open TxBD. The

HDLC controller writes CT after sending the buffer.

MPC8280 Datasheet(PDF) 1275 Page - Freescale Semiconductor, Inc

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