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MPC8280 Datasheet(PDF) 1346 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1346 Page - Freescale Semiconductor, Inc |
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1346 / 1386 page ![]() MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-2 Freescale Semiconductor Burst. A bus transfer whose data phase consists of a sequence of transfers. For example, on a 64-bit bus, a 4-beat burst can transfer four 64-bit double words. Bus parking. A feature that optimizes the use of the bus by allowing a device to retain bus mastership without having to rearbitrate. C Cache. High-speed memory component containing recently-accessed data and/or instructions (subset of main memory). Cache coherency. An attribute in which an accurate and common view of memory is provided to all devices that share a memory system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor’s cache. Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. This operation is generated typically by a Data Cache Block Flush (dcbf) instruction. Caching-inhibited. A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. Cast-outs. Cache blocks that must be written to memory when a cache miss causes a cache block to be replaced. Changed bit. One of two page history bits found in each page table entry (PTE). The processor sets the changed bit if any store is performed into the page. See also Page access history bits and Referenced bit. Clear. To cause a bit or bit field to register a value of zero. The opposite of 'set'. Context synchronization. An operation that ensures that all instructions in execution complete past the point where they can produce an exception, that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain events occur (such as an exception). Copy-back. An operation in which modified data in a cache block is copied back to memory. Critical-data first. An aspect of burst accesses that allow the requested data (typically a word or double word) in a cache block to be transferred first. D Denormalized number. A nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose explicit or implicit leading significand bit is zero. |
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