MPC8280 datasheet(1347/1386 Pages) FREESCALE

1347 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-3

Direct-mapped cache. A cache in which each main memory address can appear in only

one location within the cache. Operates more quickly when the memory request is

a cache hit.

Direct-store. Interface available on processors that implement the PowerPC architecture

only to support direct-store devices from the POWER architecture. When the T bit

of a segment descriptor is set, the descriptor defines the region of memory that will

be a direct-store segment. Note that this facility is being phased out of the

architecture and will not likely be supported in future devices. Therefore, software

should not depend on it and new software should not use it.

Effective address (EA). The 32- or 64-bit address specified for a load, store, or an

instruction fetch. This address is then submitted to the MMU for translation to

either a physical memory address or an I/O address.

Exception. A condition encountered by the processor that requires special, supervisor-level

processing.

Exception handler. A software routine that executes when an exception is taken.

Normally, the exception handler corrects the condition that caused the exception,

or performs some other meaningful task (that may include aborting the program

that caused the exception). The address for each exception handler is identified by

an exception vector offset defined by the architecture and a prefix selected via the

MSR.

Extended opcode. A secondary opcode field generally located in instruction bits 21–30

that further defines the instruction type. All PowerPC instructions are one word in

length. The most significant 6 bits of the instruction are the primary opcode,

identifying the type of instruction. See also Primary opcode.

Execution synchronization. A mechanism by which all instructions in execution are

architecturally complete before beginning execution (appearing to begin

execution) of the next instruction. Similar to context synchronization but doesn't

force the contents of the instruction buffers to be deleted and refetched.

Exponent. In the binary representation of a floating-point number, the exponent is the

component that normally signifies the integer power to which the value 2 is raised

in determining the value of the represented number. See also Biased exponent.

Fetch. Retrieving instructions from either the cache or main memory and placing them into

the instruction queue.

Fully-associative. Addressing scheme in which every cache location (every byte) can have

any possible address.

General-purpose register (GPR). Any of the 32 registers in the general-purpose register

file. These registers provide the source operands and destination results for all

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