MPC8280 datasheet(1348/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Glossary-4

Freescale Semiconductor

integer data manipulation instructions. Integer load instructions move data from

memory to GPRs and store instructions move data from GPRs to memory.

Harvard architecture. An architectural model featuring separate caches for instructions

and data.

IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that

defines operations and representations of binary floating-point arithmetic.

Illegal instructions. A class of instructions that are not implemented for a particular

processor that implement the PowerPC architecture. These include instructions

not defined by the PowerPC architecture. In addition, for 32-bit implementations,

instructions that are defined only for 64-bit implementations are considered to be

illegal instructions. For 64-bit implementations instructions that are defined only

for 32-bit implementations are considered to be illegal instructions.

Implementation. A particular processor that conforms to the PowerPC architecture, but

may differ from other architecture-compliant implementations (for example, in

design, feature set, and implementation of optional features). The PowerPC

architecture has many different implementations.

Implementation-dependent. An aspect of a feature in a processor’s design that is defined

by a processor’s design specifications rather than by the PowerPC architecture.

Implementation-specific. An aspect of a feature in a processor’s design that is not required

by the PowerPC architecture, but for which the PowerPC architecture may provide

concessions to ensure that processors that implement the feature do so

consistently.

Imprecise exception. A type of synchronous exception that is allowed not to adhere to the

precise exception model (See also Precise exception). The PowerPC architecture

allows only floating-point exceptions to be handled imprecisely.

Internal bus. The bus connecting the core and system interface unit (SIU).

Instruction latency. The total number of clock cycles necessary to execute an instruction

and make ready the results of that instruction.

Interrupt. An asynchronous exception. On PowerPC processors, interrupts are a special

case of exceptions. See also Asynchronous exception.

Latency. Time that an operation requires. For example, execution latency is the number of

processor clocks an instruction takes to execute. Memory latency is the number of

bus clocks needed to perform a memory operation.

Least-significant bit (lsb). The bit of least value in an address, register, data element, or

instruction encoding.

MPC8280 Datasheet(PDF) 1348 Page - Freescale Semiconductor, Inc