MPC8280 datasheet(1351/1386 Pages) FREESCALE

1351 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-7

Protection boundary. Boundary between protection domains.

Protection domain. A protection domain is a segment, a virtual page, a BAT area, or a

range of unmapped effective addresses. It is defined only when the appropriate

relocate bit in the MSR (IR or DR) is 1.

Quad word. A group of 16 contiguous locations starting at an address divisible by 16.

rA. Instruction field that specifies a GPR to be used as a source or destination.

rB. Instruction field that specifies a GPR to be used as a source.

rD. Instruction field that specifies a GPR to be used as a destination.

rS. Instruction field that specifies a GPR to be used as a source.

Real address mode. An MMU mode when no address translation is performed and the

effective address specified is the same as the physical address. The processor’s

MMU is operating in real address mode if its ability to perform address translation

was disabled through the MSR registers IR or DR bits.

Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When set, it updates the

condition register (CR) to reflect the result of the operation.

the address for the load or store.

an immediate value to be added to the contents of a specified GPR to form the

target address for the load or store.

contents of two GPRs be added together to yield the target address for the load or

store.

Reservation. The processor establishes a reservation on a cache block of memory space

when it executes an lwarx instruction to read a memory semaphore into a GPR.

Reserved field. In a register, a reserved field is one that is not assigned a function. A

reserved field may be a single bit. The handling of reserved bits is

implementation-dependent. Software is permitted to write any value to such a bit.

A subsequent reading of the bit returns 0 if the value last written to the bit was 0

and returns an undefined value (0 or 1) otherwise.

RISC (reduced instruction set computing). An architecture characterized by fixed-length

instructions with nonoverlapping functionality and by a separate set of load and

store instructions that perform memory accesses.

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