MPC8280 datasheet(1350/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Glossary-6

Freescale Semiconductor

OEA (operating environment architecture). Level of the architecture that describes

PowerPC memory management model, supervisor-level registers,

synchronization requirements, and the exception model. It also defines the

time-base feature from a supervisor-level perspective. Implementations that

conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.

Optional. A feature, such as an instruction, a register, or an exception, that is defined by

the PowerPC architecture but not required to be implemented.

Out-of-order. An aspect of an operation that allows it to be performed ahead of one that

may have preceded it in the sequential model, for example, speculative operations.

An operation is said to be performed out-of-order if, at the time that it is

performed, it is not known to be required by the sequential execution model. See

In-order.

Out-of-order execution. A technique that allows instructions to be issued and completed

in an order that differs from their sequence in the instruction stream.

Overflow. An error condition that occurs during arithmetic operations when the result

cannot be stored accurately in the destination register(s). For example, if two

32-bit numbers are multiplied, the result may not be representable in 32 bits.

Pace control. Controls the rate of the data flow between a master and slave.

Page. Region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned

on a 4-Kbyte boundary.

Page fault. Condition that occurs when the processor attempts to access a memory location

that does not reside within a page not currently resident in physical memory. On

processors that implement the PowerPC architecture, a page fault exception

condition occurs when a matching, valid page table entry (PTE[V] = 1) cannot be

located.

Physical memory. The actual memory that can be accessed through the system’s memory

bus.

Pipelining. Technique that breaks operations, such as instruction processing or bus

transactions, into smaller distinct stages or tenures (respectively) so that a

subsequent operation can begin before the previous one has completed.

Precise exceptions. A category of exception for which the pipeline can be stopped so

instructions that preceded the faulting instruction can complete and subsequent

instructions can be flushed and redispatched after exception handling has

completed. See Imprecise exceptions.

Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that

identifies the type of instruction. See Secondary opcode.

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