MPC8280 datasheet(1357/1386 Pages) FREESCALE

1357 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Index-3

GFMR register, 31-88

global mode entry (GMODE), 31-40

internal rate mode, 31-6

interrupt queues, 31-82

maximum performance configuration, 31-101

OAM performance monitoring, 31-29, 31-62

OAM support, 31-27

operations and maintenance (OAM) support, 31-27

overview, 31-4

parameter RAM, 31-36

performance monitoring, 31-8

performance, maximum (configuration), 31-101

programming model, 31-88

receive connection table (RCT)

AALn protocol-specific RCTs, 31-46, 31-46–??, 31-49

ATM channel code, 31-41

overview, 31-41

raw cell queue, 31-18

RCT entry format, 31-43

registers, 31-88

RxBD, 31-71

RxBD extension, 31-76

SRTS generation using external logic, 31-100

transmit connection table (TCT)

AALn protocol-specific TCTs, 31-55

ATM channel code, 31-41

overview, 31-41

TCT entry format, 31-50

transmit connection table extension (TCTE)

ABR protocol-specific, 31-59

ATM channel code, 31-41

overview, 31-41

UBR+ protocol-specific, 31-58

VBR protocol-specific, 31-57

transmit rate modes, 31-6

TxBD, 31-76

TxBD extension, 31-80

UDC extended address mode, 31-32

UEAD_OFFSET determination, 31-39

UNI statistics table, 31-81

user-defined cells (UDC)

extended address mode, 31-32

overview, 31-32

RxBD extension (AAL5/AAL1), 31-76

TxBD extension (AAL5/AAL1), 31-80

user-defined RxBD extension (AAL5/AAL1), 31-76

user-defined TxBD extension (AAL5/AAL1), 31-80

UTOPIA interface, 31-84

VCI filtering, 31-39

VCI/VPI address lookup, 31-13

VC-level address compression tables (VCLT), 31-17

VP-level address compression table (VPLT), 31-16

Baud-rate generator (BRG)

BRGCLK, 40-2

memory map, 3-18

BCR (bus configuration register), 4-26

BDLE (SCC BISYNC DLE) register, 23-8

BISYNC mode

commands, 23-4

control character recognition, 23-5

error handling, 23-9

frame reception, 23-3

frame transmission, 23-2

overview, 23-1

parameter RAM, 23-3

programming example, 23-18

programming the controller, 23-17

receiving synchronization sequence, 23-9

RxBD, 23-12

sending synchronization sequence, 23-9

TxBD, 23-14

block diagram

dual-port RAM, 14-20

system PLL,, 10-6

Block diagrams

cascaded mode, 18-3

communications processor (CP), 14-7

communications processor module (CPM), 14-3

CPM multiplexing logic (CMX), 16-2

DPLL receiver, 20-21

dual-bus architecture, 11-2

Fast Ethernet, 36-2

FCC overview, 30-3

2C controller, 40-1

IEEE 1149.1 test access port, 1-2

parallel I/O ports, 41-6

SCC block diagram, 20-2

serial interface, 15-2

serial peripheral interface (SPI), 39-1

system interface unit (SIU)

periodic interrupt timer, 4-5

SIU block diagram, 4-1

software watchdog timer, 4-7

system configuration/protection logic, 4-3

time counter (TMCNT), 4-5

timers, 18-1

Branch processing unit, 2-6

BRGCLK, 40-2

BRn (base registers), 11-13

BSYNC (BISYNC SYNC) register, 23-7

BUFCMD (external address and command buffers), 11-42

Buffer

SPI buffer descriptor ring, 27-22

MPC8280 Datasheet(PDF) 1357 Page - Freescale Semiconductor, Inc

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