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MPC8280 Datasheet(PDF) 1360 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1360 Page - Freescale Semiconductor, Inc |
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1360 / 1386 page ![]() MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-6 Freescale Semiconductor buffer descriptors, 14-24 overview, 14-20 parameter RAM, 14-25 fast communications controllers (FCCs) Fast Ethernet mode address recognition, 36-15 block diagram, 36-2 CAM interface, 36-8 collision handling, 36-18 connecting to the MPC8280, 36-4 error handling, 36-18 FCCE, 36-21 FCCM, 36-21 features list, 36-2 FPSMR, 36-19 frame reception, 36-6 frame transmission, 36-5 hash table algorithm, 36-17 hash table effectiveness, 36-17 interpacket gap time, 36-18 interrupt events, 36-24 loopback mode, 36-18 parameter RAM, 36-8 programming model, 36-12 registers, 36-19 RMON support, 36-14 RxBD, 36-24 TxBD, 36-27 HDLC mode bit stuffing, 37-1 error control, 37-1 error handling, 37-6 FCCE, 37-14 FCCM, 37-14 FCCS, 37-16 features list, 37-1 FPSMR, 37-7 frame reception, 37-3 frame transmission, 37-2 overview, 37-1 parameter RAM, 37-3 programming model, 37-5 receive commands, 37-6 reception errors, 37-6 RxBD, 37-9 transmission errors, 37-6 transmit commands, 37-5 TxBD, 37-12 overview block diagram, 30-3 disabling FCCs, 30-20 FCCEx, 30-15 FCCMx, 30-15 FCCSx, 30-15 FCRx, 30-14 FDSRx, 30-8 FPSMRx, 30-8 FTODRx, 30-9 GFMRx, 30-3 initialization, 30-15 interrupt handling, 30-16 interrupts, 30-14 overview, 30-1 parameter RAM, 30-12 RxBD, 30-10 saving power, 30-22 switching protocols, 30-22 timing control, 30-17 TxBD, 30-10 transparent mode achieving synchronization, 38-2 external synchronization signals, 38-3 features list, 38-1 in-line synchronization pattern, 38-2 receive operation, 38-2 synchronization example, 38-3 transmit operation, 38-2 features list, 14-1 I 2C controller block diagram, 40-1 BRGCLK, 40-2 clocking and pin functions, 40-2 commands, 40-11 features list, 40-2 loopback testing, 40-4 master read (slave write), 40-4 master write (slave read), 40-3 multi-master considerations, 40-5 parameter RAM, 40-9 programming model, 40-5 registers, 40-5 RxBD, 40-12 slave read (master write), 40-3 slave write (master read), 40-4 transfers, 40-2 TxBD, 40-13 IDMA emulation auto buffer, 19-15 buffer chaining, 19-15 buffers, 19-23 bus exceptions, 19-27 commands, 19-26 controlling 60x bus bandwidth, 19-11 DACKx, 19-13 |
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