MPC8280 datasheet(1380/1386 Pages) FREESCALE

1380 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Index-26

Freescale Semiconductor

received, TC_RCCx, 35-12

transmitted, TC_TCCx, 35-12

features, 35-1

functionality, 35-3

ATM cell functions

2-cell FIFO, 35-6

receive, 35-4

transmit, 35-6

UTOPIA interface

receive, 35-7

transmit, 35-7

implementation example, 35-15

operating at higher frequencies, 35-16

programming a T1 application, 35-16

step 1, 35-17

step 2, 35-17

step 3, 35-17

step 4, 35-17

step 5, 35-17

step 6, 35-18

step 7, 35-18

programming and operating the TC layer, 35-13

programming FCC2, 35-13

programming mode, 35-7

signals, 35-7

TCN (timer counter registers), 18-7

TCn (transfer code) signals, 8-12

TCR (timer capture registers), 18-7

TDM,, 16-1

TER (timer event registers), 18-7

Terminology conventions, 1-lxxxvii

TESCRx (60x bus error status and control registers), 4-40,

11-33

TFCR (Tx buffer function code register)

overview, 20-15

TGCR (timer global configuration registers), 18-3

Timers

block diagram, 18-1

bus monitoring, 18-3

cascaded mode block diagram, 18-3

features, 18-1

general-purpose units, 18-2

pulse measurement, 18-3

Time-slot assigner

connecting to the TSA, 15-7

Time-slot assigner (TSA)

synchronization in transparent mode, 24-6

Timing

SCC timing, controlling, 20-17

TM_CMD (RISC timer command) register, 14-29

TMCNT (time counter register), 4-45

TMCNTAL (time counter alarm register), 4-46

TMCNTSC (time counter status and control register), 4-44

TMR (timer mode registers), 18-5

TODR (transmit-on-demand register)

AppleTalk mode, 26-4

overview, 20-10

TOSEQ (transmit out-of-sequence) register, 21-9

Transmission convergence (TC) layer, 35-1

Transparent mode

achieving synchronization, 24-3

commands, 24-7

DSR receiver SYNC pattern lengths, 24-3

end of frame detection, 24-6

error handling, 24-8

fast communications controllers (FCCs)

features list, 38-1

receive operation, 38-2

synchronization

achieving, 38-2

example, 38-3

external signals, 38-3

in-line pattern, 38-2

transmit operation, 38-2

frame reception, 24-2

frame transmission, 24-2

inherent synchronization, 24-6

in-line synchronization, 24-6

overview, 24-1

programming example, 24-13

RxBD, 24-9

serial management controllers (SMCs)

features list, 28-20

overview, 28-20

parameter RAM, 28-6

reception process, 28-21

synchronization signals, 24-3

synchronization, user-controlled, 24-5

transmit synchronization, 24-3

TxBD, 24-10

TRR (timer reference registers), 18-6

TSIZn (transfer size) signals, 8-12

TSTATE (internal transmitter state) register, 29-7

TTn (transfer type) signals, 8-9

UART mode

commands, 21-6

control character insertion, 21-9

data handling, character and message-based, 21-5

error reporting, 21-5

features list, 21-2

fractional stop bits, 21-10

handling errors, 21-11

MPC8280 Datasheet(PDF) 1380 Page - Freescale Semiconductor, Inc

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