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MPC8280 Datasheet(PDF) 1377 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1377 Page - Freescale Semiconductor, Inc |
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1377 / 1386 page  MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-23 error handling, 22-5 features list, 22-1 GSMR, HDLC bus protocol programming, 22-22 interrupts, 22-13 memory map, 22-3 multi-master bus configuration, 22-17 overview, 22-1 parameter RAM, 22-3 performance, increasing, 22-19 programming example, 22-14, 22-22 programming the controller, 22-4 PSMR, 22-7 RxBD, 22-8 single-master bus configuration, 22-18 TxBD, 22-11 using the TSA, 22-21 overview buffer descriptors, 20-10 controlling SCC timing, 20-17 DPLL operation, 20-21 features, 20-2 initialization, 20-16 interrupt handling, 20-16 parameter RAM, 20-13 reconfiguration, 20-24 reset sequence, 20-25 switching protocols, 20-25 transparent mode achieving synchronization, 24-3 commands, 24-7 DSR receiver SYNC pattern lengths, 24-3 end of frame detection, 24-6 error handling, 24-8 frame reception, 24-2 frame transmission, 24-2 inherent synchronization, 24-6 in-line synchronization, 24-6 overview, 24-1 programming example, 24-13 RxBD, 24-9 synchronization signals, 24-3 synchronization, user-controlled, 24-5 transmit synchronization, 24-3 TxBD, 24-10 UART mode commands, 21-6 control character insertion, 21-9 data handling, character and message-based, 21-5 error reporting, 21-5 features list, 21-2 fractional stop bits, 21-10 handling errors, 21-11 hunt mode, 21-9 normal asynchronous mode, 21-2 overview, 21-1 parameter RAM, 21-3 programming example, 21-22 RxBD, 21-14 S-records loader application, 21-23 status reporting, 21-5 synchronous mode, 21-3 TxBD, 21-18 Serial configuration, 14-3 Serial interface (SI) enabling connections, 15-7 features, 15-3 GCI support, 15-31 IDL bus implementation programming the IDL, 15-29 IDL interface support, 15-25 overview, 15-4 programming GCI, 15-33 programming RAM entries, 15-10 registers, 15-17 see also CPM multiplexing logic (CMX) SI RAM, 15-8 Serial management controllers (SMCs) buffer descriptors, overview, 28-4 disabling SMCs on-the-fly, 28-8 disabling the receiver, 28-9 disabling the transmitter, 28-9 enabling the receiver, 28-9 enabling the transmitter, 28-9 features list, 28-2 GCI mode C/I channel handling the SMC, 28-32 reception process, 28-32 RxBD, 28-34 transmission process, 28-32 TxBD, 28-34 commands, 28-33 monitor channel reception process, 28-31 RxBD, 28-33 transmission process, 28-31 TxBD, 28-33 overview, 28-30 parameter RAM, 28-31 memory structure, 28-5 mode selection, 28-2 NMSI connection, receive and transmit, 28-2 parameter RAM GCI mode, 28-31 |
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