TMP88CS38 datasheet(34/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-34

1.6.2

Address-trap-reset

If the CPU should start looping for some cause such as noise and an attempt be made to

fetch an instruction from the on-chip RAM, DBR or the SFR area, address-trap-reset will

be generated. Then, the RESET pin output will go low. The reset time is about 8/fc to 24/fc

[s] (0.5 to 1.5

μs at 16 MHz).

Note 1:

≤ a ≤ 008BFH (TMP88CS38), 0 ≤ a ≤ 006BFH (TMP88CM38A/CP38A)

≤ a ≤ 002BFH (The ROM corrective function is enabled.)

Note 2:

During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.

Figure 1.6.2 Address-trap-reset

1.6.3

Watchdog Timer Reset

Refer to section 2.4 “Watchdog Timer”.

1.6.4

System-clock-reset

Clearing bits 7 in SYSCR2 to “0”, system clock stops and causes the microcomputer to

deadlock. This can be prevented by automatically generating a reset signal whenever bits 7,

6 and 5 in SYSCR2

= 000 is detected to continue the oscillation. The RESET pin output

goes low from high-impedance. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5

μs at 16

MHz).

Instruction

execution

RESET

output

Reset release

Instruction at address

Address trap is occurred

(“L” output)

8/fc to 24/fc [s]

4/fc

12/fc [s]

20/fc [s]

(High-Z)

(No wait)

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