TMP88CS38 datasheet(8/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-8

1.2

Program Memory (ROM)

The TMP88CS38 contains a 64-Kbyte program memory (Mask ROM) at addresses from

04000H to 13EFFH and FFF00H to FFFFFH.

The TMP88CM38A contains a 32-Kbyte program memory (Mask ROM) at address from

04000H to 0BEFFH and FFF00H to FFFFFH. The TMP88CP38A contains a 48-Kbyte program

memory (Mask ROM) at address from 04000H to 0FEFFH and FFF00H to FFFFFH.

Addresses FFF00H through FFFFFH in the program memory are also used for a particular

purpose.

1.3

Data Memory (RAM)

The TMP88CS38 has a 2-Kbyte data memory (Static RAM) address from 0040H to 08BFH.

The TMP88CM38A/P38A has a 1.5-Kbyte data memory (Static RAM) (Address from 0040H to

06BFH.

The first 128 bytes (Addresses 00040H through 000BFH) in the built-in RAM are also

available as general-purpose register banks.

The general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the

current bank addresses.

Example: Clears RAM to “00H” except the bank 0 (TMP88CS38/CM38A/CP38A):

HL, 0048H

;

Sets start address to HL register pair

A, H

;

Sets initial data (00H) to A register

BC, 0877H

;

Sets number of byte to BC register pair

SRAMCLR:

(HL+), A

DEC

JRS

F, SRAMCLR

Note:

The data memory contents become unstable when the power supply is turned on ; therefore,

the data memory should be initialized by an initialization routine. Note that the

general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the

current bank addresses.

1.4

System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby

controller.

Figure 1.4.1 System Clock Controller

00036H

Timing generator control register

00038H

XOUT

XIN

System clocks

Timing

generator

High-frequency

clock oscillator

Standby controller

Clock generator control

System control registers

SYSCR1

00039H

SYSCR2

TBTCR

Clock

generator

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