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TMP88CS38 Datasheet(PDF) 27 Page - Toshiba Semiconductor |
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TMP88CS38 Datasheet(HTML) 27 Page - Toshiba Semiconductor |
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27 / 226 page  TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-27 Note 1: a: Return address, b: Entry address, c: Address which the RETI instruction is stored Note 2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is 62/fc [s] with interrupt enabled. Figure 1.5.3 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction n n − 1n −2n − 3n − 4n − 5 a a + 1 a b b + 2 b + 1 b + 3 b + 2 b + 1 b n − 4 n − 3 n − 2 n − 1 n FFFE4 a + 1 a FFFE5 FFFE6 FFFE7 k = i + (FFFE7H). 3 − 0 i Instruction Interrupt acceptance Instruction (a) Interrupt acceptance IMF Execution Address bus PC SP RBS IL6 IL15 INTTBT INT5 1-machine cycle Interrupt service task INF a + 1 c c + 1n − 4n − 3n − 2n − 1n a n − 5 n − 4n − 3n − 2n − 1n IMF Execution Address bus PC SP RBS (b) Return from interrupt instruction a + 2 a C + 2 c + 1 c i k RETI instruction a + 1 Interrupt service task INF |
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