TMP88CS38 datasheet(25/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-25

Interrupt Latches (IL)

IL31

IL30

IL29

IL28

IL27

IL26

IL25

IL24

IL23

IL22

IL21

IL20

IL19

IL18

IL17

IL16

(0002E,

0002FH)

ILD (0002FH)

ILE (0002EH)

(Initial value: 00000000 00000000)

IL15

IL14

IL13

IL12

IL11

IL10

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

INF

(0003C,

0003DH)

ILH (0003DH)

ILL (0003CH)

(Initial value: 00000000 00000000**)

Interrupt Enable Registers (EIR)

EF31 EF30 EF29 EF28 EF27 EF26 EF25 EF24 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16

EIR

(0002C,

0002DH)

EIRD (0002DH)

EIRE (0002CH)

(Initial value: 00000000 00000000)

EF15 EF14 EF13 EF12 EF11 EF10

EF9

EF8

EF7

EF6

EF5

EF4

EF3

IMF

EIR

(0003A,

0003BH)

EIRH (0003BH)

EIRL (0003AH)

(Initial value: 00000000 0000000**0)

Note 1:

Do not clear IL with read-modify-write instructions such as bit operations.

Note 2:

Do not set IMF to “1” during non-maskable interrupt service program.

Note 3:

Bits 1 and 0 in ILL are read in as undefined data when a read instruction is executed.

Note 4:

*: Don’t care

Note 5:

Do not clear IL2 to “0” by an instruction.

Note 6:

At TMP88CS38/CM38A/CP38A, IL18 to IL31 and IF18 to IF31 are not used.

Note 7:

After IMF is cleared, modify EF and IL.

Figure 1.5.2 Interrupt Latches (IL) and Interrupt Enable Registers (EIR)

1.5.1

Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is

cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 12

machine cycles (3

μs at fc = 16 MHz in the NORMAL mode) after the completion of the

current instruction execution. The interrupt service task terminates upon execution of an

interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo

non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance

processing.

(1) Interrupt acceptance

Interrupt acceptance processing is as follows.

1. The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the

acceptance of any following maskable interrupts. When a non-maskable interrupt

is accepted, the acceptance of any following interrupts is temporarily disabled.

2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.

3. The contents of the program counter (PC) and the program status word (PSW) are

saved (Pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL. The

stack pointer (SP) is decremented five times.

4. The entry address of the interrupt service program is read from the vector table,

and set to the program counter.

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