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TMP88CS38 Datasheet(PDF) 43 Page - Toshiba Semiconductor

Part # TMP88CS38
Description  8-bit single chip microcomputer
PDF  226 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS38 Datasheet(HTML) 43 Page - Toshiba Semiconductor

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TMP88CS38/CM38A/CP38A
2007-09-12
88CS38-43
Address
Read
Write
00F80H
ORDON (OSD control)
81
−
OSD control register
−
OSD control register
A1
ORCLKC (OSD clock status)
ORCLKF (OSD clock control)
A2
−
OSD control register
−
OSD control register
B9
ORIRC (OSD display counter)
ORIRC (OSD interrupt control)
BA
−
OSD control register
−
OSD control register
C0
Reserved
Reserved
D0
IDLEINV (Key-on wakeup status)
IDLECR (Key-on wakeup control)
D1
Reserved
Reserved
D8
SINTCR (Data slicer interrupt control)
D9
−
DACLCR (Sync. tip slice level setting)
DA
SLVLCR (Slice level control)
DB
SIFDR1 (Caption data 1st byte)
−
DC
SIFDR2 (Caption data 2nd byte)
−
DD
SIFSR (Data slicer status)
−
DE
−
−
DF
SIFS1R (Data slicer status 2)
SIFSMS1 (Data slicer mode setting)
E0
ROMCCR (ROM corrective control)
E1
ROMCSR (ROM corrective status)
−
E2
−
ROMCDR (ROM corrective data)
E3
Reserved
E4
JECR (Jitter elimination control)
E5
JESR (Jitter elimination status)
−
E6
−
TVSCR (Test video signal output)
E7
Reserved
E8
RXCR1 (Remote control receive control 2)
E9
RXCR2 (Remote control receive control 1)
EA
RXCTR (Remote control receive counter)
−
EB
RXDBR (Remote control receive data buffer)
−
EC
RXSR (Remote control status)
−
ED
Reserved
EE
FC8CR (FC8 control)
EF
Reserved
F0
Reserved
F1
SCCRB (Serial clock source control)
SCSR (Serial clock source status)
F2
Reserved
F3
Reserved
F4
Reserved
F5
−
PWMCR2A (PWM control 2A)
F6
−
PWMCR2B (PWM control 2B)
F7
−
PWMDBR2 (PWM data buffer)
F8
Reserved
Reserved
FE
−
PSELCR (P3, P5 control 2)
FF
Reserved
(b) Data buffer registers
Note 1:
Do not access reserved areas by the program.
Note 2:
−: Cannot be accessed.
Note 3:
Write-only registers cannot use the read-modify-write instructions (Bit manipulation instructions such as
SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Figure 2.1.2 (b) DBR



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