TMP88CS38 datasheet(30/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-30

(3) Interrupt return

The interrupt return instructions [RETI]/[RETN] perform the following operations.

[RETI] Maskable Interrupt Return

[RETN] Non-maskable Interrupt Return

1. The contents of the program counter and

the program status word are restored

from the stack.

1. The contents of the program counter and program status

word are restored from the stack.

2. The stack pointer is incremented 5 times. 2. The stack pointer is incremented 5 times.

3. The interrupt master enable flag is set to

“1”.

3. The interrupt master enable flag is set to “1” only when a

non-maskable interrupt is accepted in interrupt enable status.

However, the interrupt master enable flag remains at “0”

when so clear by an interrupt service program.

4. The interrupt nesting counter is

decremented, and the interrupt nesting

flag is changed.

4. The interrupt nesting counter is decremented, and the

interrupt nesting flag is changed.

Interrupt requests are sampled during the final cycle of the instruction being

executed. Thus, the next interrupt can be accepted immediately after the interrupt

return instruction is executed.

Note:

When the interrupt processing time is longer than the interrupt request generation

time, the interrupt service task is performed but not the main task.

1.5.2

Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts

interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a

non-maskable interrupt is already underway, executing the SWI instruction will not

generate a software interrupt but will result in the same operation as the [NOP]

instruction.

Use the [SWI] instruction only for detection of the address error or for debugging.

1. Address error detection

FFH is read if for some cause such as noise the CPU attempts to fetch an instruction

from a non-existent memory address. Code FFH is the SWI instruction, so a software

interrupt is generated and an address error is detected. The address error detection

range can be further expanded by writing FFH to unused areas of the program memory.

Address-trap reset is generated in case that an instruction is fetched from RAM, SFR

or DBR areas.

2. Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software

break point setting address.

1.5.3

External Interrupts

The TMP88CS38/CM38A/CP38A each have five external interrupt inputs ( INT0 , INT2,

INT3, INT4, and INT5 ). Three of these are equipped with digital noise rejection circuits

(Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also

possible with INT2, INT3 and INT4.

The INT0 /P50 pin can be configured as either an external interrupt input pin or an

input/output port, and is configured as an input port during reset.

Edge selection, noise rejection control except INT3 pin input and INT0 /P50 pin function

selection are performed by the external interrupt control register (EINTCR). Edge selecting

and noise rejection control for INT3 pin input are preformed by the remote control signal

preprocessor control registers. (Refer to the section of the remote control signal

preprocessor.) When INT0EN

= 0, the IL3 will not be set even if the falling edge of INT0

pin input is detected.

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