 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M68HC08 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
M68HC08 Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc |
|
|
24 / 172 page  Memory MC68HC908JL3E Family Data Sheet, Rev. 3 24 Freescale Semiconductor $001C Unimplemented Read: Write: $001D IRQ Status and Control Register (INTSCR) Read: 0000 IRQF1 0 IMASK1 MODE1 Write: ACK1 Reset: 00000000 $001E Configuration Register 2 (CONFIG2)† Read: IRQPUD RR LVIT1 LVIT0 RRR Write: Reset: 000 0* 0* 000 $001F Configuration Register 1 (CONFIG1)† Read: COPRS R R LVID R SSREC STOP COPD Write: Reset: 00000000 † One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only. $0020 TIM Status and Control Register (TSC) Read: TOF TOIE TSTOP 00 PS2 PS1 PS0 Write: 0 TRST Reset: 00100000 $0021 TIM Counter Register High (TCNTH) Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Write: Reset: 00000000 $0022 TIM Counter Register Low (TCNTL) Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Write: Reset: 00000000 $0023 TIM Counter Modulo Register High (TMODH) Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Write: Reset: 11111111 $0024 TIM Counter Modulo Register Low (TMODL) Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Write: Reset: 11111111 $0025 TIM Channel 0 Status and Control Register (TSC0) Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write: 0 Reset: 00000000 $0026 TIM Channel 0 Register High (TCH0H) Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Write: Reset: Indeterminate after reset $0027 TIM Channel 0 Register Low (TCH0L) Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Write: Reset: Indeterminate after reset $0028 TIM Channel 1 Status and Control Register (TSC1) Read: CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX Write: 0 Reset: 00000000 $0029 TIM Channel 1 Register High (TCH1H) Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Write: Reset: Indeterminate after reset $002A TIM Channel 1 Register Low (TCH1L) Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Write: Reset: Indeterminate after reset Addr. Register Name Bit 7 654321 Bit 0 = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 4) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
