M68HC08 datasheet(79/172 Pages) FREESCALE

79 / 172 page

Functional Description

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

When the host computer has completed downloading code into the MCU RAM, the host then sends a

RUN command, which executes an RTI, which sends control to the address on the stack pointer.

7.3.2 Baud Rate

The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud

rate if entry to monitor mode is by IRQ1 = VDD +VHI. When PTB3 is high, the divide by ratio is 1024. If

the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.

7.3.3 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.

(See Figure 7-3 and Figure 7-4.)

Figure 7-3. Monitor Data Format

Table 7-2. Monitor Mode Vector Differences

Modes

Functions

COP

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

User

Enabled

$FFFE

$FFFF

$FFFC

$FFFD

$FFFC

$FFFD

Monitor

Disabled(1)

$FEFE

$FEFF

$FEFC

$FEFD

$FEFC

$FEFD

Notes:

1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM

asserts its COP enable output. The COP is a mask option enabled or disabled by the

COPD bit in the configuration register.

Table 7-3. Monitor Baud Rate Selection

Monitor Mode

Entry By:

Input Clock

Frequency

PTB3

Baud Rate

IRQ1 = VDD + VHI

4.9152 MHz

9600 bps

9.8304 MHz

9600 bps

4.9152 MHz

4800 bps

Blank reset vector,

IRQ1 = VDD

9.8304 MHz

9600 bps

4.9152 MHz

4800 bps

BIT 5

START

BIT

BIT 0

BIT 1

STOP

BIT

START

BIT

BIT 2

BIT 3

BIT 4

BIT 6

BIT 7

M68HC08 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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