M68HC08 datasheet(64/172 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

IF14 — Interrupt Flags

This flag indicates the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present

0 = No interrupt request present

Bit 0 to 6 — Always read 0

5.5.2.3 Interrupt Status Register 3

IF15 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present

0 = No interrupt request present

Bit 1 to 7 — Always read 0

5.5.3 Reset

All reset sources always have equal and highest priority and cannot be arbitrated.

5.5.4 Break Interrupts

The break module can stop normal program flow at a software-programmable break point by asserting its

break interrupt output. (See Chapter 15 Break Module (BREAK).) The SIM puts the CPU into the break

state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to

see how each module is affected by the break state.

5.5.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The

user can select whether flags are protected from being cleared by properly initializing the break clear flag

enable bit (BCFE) in the break flag control register (BFCR).

Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This

protection allows registers to be freely read and written during break mode without losing status flag

information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains

cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,

a read of one register followed by the read or write of another — are protected, even when the first step

is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step

will clear the flag as normal.

Address:

$FE06

Bit 7

654321

Bit 0

Read:

0000000

IF15

Write:

RRRRRRRR

Reset:

00000000

R= Reserved

Figure 5-14. Interrupt Status Register 3 (INT3)

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