M68HC08 datasheet(90/172 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect

operation for up to two PWM periods. For example, writing a new value before the counter reaches the

old value but after the counter reaches the new value prevents any compare during that PWM period.

Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the

compare to be missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:

•

When changing to a shorter pulse width, enable channel x output compare interrupts and write the

new value in the output compare interrupt routine. The output compare interrupt occurs at the end

of the current pulse. The interrupt routine has until the end of the PWM period to write the new

value.

•

When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in

the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM

period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)

could cause two output compares to occur in the same PWM period.

NOTE

In PWM signal generation, do not program the PWM channel to toggle on

output compare. Toggling on output compare prevents reliable 0% duty

cycle generation and removes the ability of the channel to self-correct in the

event of software error or noise. Toggling on output compare also can

cause incorrect PWM signal generation when changing the PWM pulse

width to a new, much larger value.

8.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.

The TIM channel registers of the linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.

The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel

1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning

of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the

pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM

channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,

TCH1, is available as a general-purpose I/O pin.

NOTE

In buffered PWM signal generation, do not write new pulse width values to

the currently active channel registers. User software should track the

currently active channel to prevent writing a new value to the active

channel. Writing to the active channel registers is the same as generating

unbuffered PWM signals.

8.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered PWM signals, use the following

initialization procedure:

In the TIM status and control register (TSC):

Stop the TIM counter by setting the TIM stop bit, TSTOP.

Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.

M68HC08 Datasheet(PDF) 90 Page - Freescale Semiconductor, Inc

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