M68HC08 datasheet(67/172 Pages) FREESCALE

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SIM Registers

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

Figure 5-19. Stop Mode Recovery from Interrupt or Break

5.7 SIM Registers

The SIM has three memory mapped registers. Table 5-4 shows the mapping of these registers.

5.7.1 Break Status Register (BSR)

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break

interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt

0 = Stop mode or wait mode was not exited by break interrupt

SBSW can be read within the break state SWI routine. The user can modify the return address on the

stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit

clears it.

Table 5-4. SIM Registers

Address

Access Mode

$FE00

BSR

User

$FE01

RSR

User

$FE03

BFCR

User

Address:

$FE00

Bit 7

654321

Bit 0

Read:

RRRRRR

SBSW

Write:

Note(1)

Reset:

= Reserved

1. Writing a logic zero clears SBSW.

Figure 5-20. Break Status Register (BSR)

2OSCOUT

INT/BREAK

IAB

STOP + 2

SP – 1

SP – 2

SP – 3

STOP +1

STOP RECOVERY PERIOD

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