M68HC08 datasheet(27/172 Pages) FREESCALE

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Random-Access Memory (RAM)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

2.4 Random-Access Memory (RAM)

Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable.

The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.

NOTE

For correct operation, the stack pointer must point only to RAM locations.

Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page

zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved

from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero

RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global

variables.

Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU

registers.

NOTE

For M6805 compatibility, the H register is not stacked.

During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack

pointer decrements during pushes and increments during pulls.

NOTE

Be careful when using nested subroutines. The CPU may overwrite data in

the RAM during a subroutine or during the interrupt stacking operation.

2.5 FLASH Memory

This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be

read, programmed, and erased from a single external supply. The program and erase operations are

enabled through the use of an internal charge pump.

Device

FLASH Memory Size

(Bytes)

Memory Address Range

MC68H(R)C908JL3E

4,096

$EC00—$FBFF

MC68H(R)C908JK3E

4,096

$EC00—$FBFF

MC68H(R)C908JK1E

1,536

$F600—$FBFF

Addr.

Bit 7

654321

Bit 0

$FE08

FLASH Control Register

(FLCR)

Read:

0000

HVEN

MASS

ERASE

PGM

Write:

Reset:

00000000

$FE09

FLASH Block Protect

(FLBPR)

Read:

BPR7

BPR6

BPR5

BPR4

BPR3

BPR2

BPR1

BPR0

Write:

Reset:

00000000

= Unimplemented

Figure 2-3. FLASH I/O Register Summary

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