M68HC08 datasheet(102/172 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

MC68HC908JL3E Family Data Sheet, Rev. 3

102

Freescale Semiconductor

9.5.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.

ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the

analog circuitry before attempting a new ADC conversion after exiting stop mode.

9.6 I/O Signals

The ADC module has 12 channels that are shared with I/O port B and port D.

9.6.1 ADC Voltage In (ADCVIN)

ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module.

9.7 I/O Registers

These I/O registers control and monitor ADC operation:

•

ADC status and control register (ADSCR)

•

ADC data register (ADR)

•

ADC clock register (ADICLK)

9.7.1 ADC Status and Control Register

The following paragraphs describe the function of the ADC status and control register.

COCO — Conversions Complete Bit

When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is

completed. This bit is cleared whenever the ADC status and control register is written or whenever the

ADC data register is read. Reset clears this bit.

1 = Conversion completed (AIEN = 0)

0 = Conversion not completed (AIEN = 0)

When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always

be logic 0 when read.

AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is

cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.

1 = ADC interrupt enabled

0 = ADC interrupt disabled

Address:

$003C

Bit 7

654321

Bit 0

Read:

COCO

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Write:

Reset:

00011111

= Unimplemented

Figure 9-3. ADC Status and Control Register (ADSCR)

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