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VS6724 Datasheet(PDF) 96 Page - STMicroelectronics |
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VS6724 Datasheet(HTML) 96 Page - STMicroelectronics |
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96 / 118 page ![]() Programming model and register description VS6724 96/118 0x239d(MSByte) 0x239e(LSByte) bVsyncRisingFine Default value 0x00 Type BYTE Purpose Operates only when bVSyncSetup bit [2] = 0 0x23a1(MSByte) 0x23a2(LSByte) bVsyncFallingFineH Default value 0x00 Type BYTE Purpose Operates only when bVSyncSetup bit [2] = 0 0x23a5(MSByte) 0x23a6(LSByte) bVsyncRisingCoarse Default value 0x00 Type UINT_16 Purpose Operates only when bVSyncSetup bit [2] = 0 0x23a9MSByte) 0x23aa(LSByte) bVsyncFallingCoarseH Default value 0x01 Type BYTE Purpose Operates only when bVSyncSetup bit [2] = 0 0x23ae bSyncCodeSetup Default value 0x01 Type CODED flag bits [0] SyncCodeSetup_ins_code_en 1-> enable embedded codes 0-> disable embedded codes [1] SyncCodeSetup_frame 0=ITU-656, 1 ITU-CSI 0-> ITU-656 codes 1-> ITU-CSI codes [2] SyncCodeSetup_field_bit - ITU-656 only 1-> Next field is odd frame 0-> Next field is even frame [3] SyncCodeSetup_field_tag - ITU-656 only 1-> the sync code for odd and even frames will toggle 0 -> the sync code will be constant for all frames [4] SyncCodeSetup_field_load - ITU-656 only 1-> Load new settings for bits [3:2] 0 -> New settings for bits [3:2] not consumed Table 47. Output control (continued) Index OutputControl(1) |
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