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VS6724 Datasheet(PDF) 20 Page - STMicroelectronics |
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VS6724 Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 118 page  Functional description VS6724 20/118 Figure 8. JPEG Compression image size to squeeze value relationship 2.6.4 FIFO control The rate which the FIFO is emptied (and therefore the output PCLK frequency) can be controlled using the bOIFClkRatio register. Changing the FIFO readout rate will in turn change the FIFO’s fullness and therefore the squeeze factor used. Section 2.11.2: PLL operation on page 39 describes the calculations for PCLKmax frequency. This frequency is divided by the bOIFClkRatio to give the max JPEG PCLK output from the device: bOIFClkRatio {0x2514} 1. PCLK is 2 times slower 2. PCLK is 4 times slower 3. PCLK is 8 times slower 4. PCLK is 16 times slower 5. PCLK is 32 times slower 6. PCLK is 64 times slower Image size to squeeze relationship 0 200 400 600 800 1000 1200 1400 1600 1800 Squeeze value Scene1 Scene2 Scene3 Scene4 Scene5 Scene6 Scene7 Scene8 Scene9 Scene10 Scene11 MEAN |
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