 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VS6724 Datasheet(PDF) 111 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
VS6724 Datasheet(HTML) 111 Page - STMicroelectronics |
|
|
111 / 118 page  VS6724 Electrical characteristics 111/118 6.7 Parallel data interface timing VS6724 contains a parallel data output port (D[7:0]) and associated qualification signals (HSYNC, VSYNC, PCLK and FSO). This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 43. Parallel data output video timing Table 62. Parallel data interface timings Symbol Description Min. Max. Unit fPCLK PCLK frequency 80 MHz tPCLKL PCLK low width (1/2 * (1/fPCLK)) -1 (1/2 * (1/fPCLK)) +1 ns tPCLKH PCLK high width (1/2 * (1/fPCLK)) -1 (1/2 * (1/fPCLK)) +1 ns tDV PCLK to output valid -1 1 ns tPCLKL tPCLKH 1/fPCLK PCLK D[0:7] HSYNC, polarity = 0 tDV Valid VSYNC |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
