DAC8760IPWPR.B datasheet(25/69 Pages) TI2

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7.10 Typical Characteristics (continued)

at TA = 25°C (unless otherwise noted)

-0.12

-0.09

-0.06

-0.03

0.00

0.03

0.06

0.09

0.12

-40

-25

-10

110

125

Temperature (oC)

0 mA to 20 mA Internal RSET

0 mA to 24 mA Internal RSET

4 mA to 20 mA Internal RSET

0 mA to 20 mA External RSET

0 mA to 24 mA External RSET

4 mA to 20 mA External RSET

C007

AVDD = 10 V

AVSS = 0 V

LOAD = 300 Ÿ

Figure 7-69. IOUT Gain Error vs Temperature

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

-40

-25

-10

110

125

Temperature (oC)

C004

AVDD = 36 V

AVSS = 0 V

IOUT = 24 mA

LOAD = 300 Ÿ

Compliance voltage headroom is defined as the drop from

AVDD pin to the IOUT pin.

Figure 7-70. Compliance Headroom Voltage(1) vs Temperature

Headroom Voltage (V)

C005

AVDD = 36 V

AVSS = 0 V

LOAD = 300 Ÿ

DAC configured to deliver 24 mA

Compliance voltage headroom is defined as the drop from

AVDD pin to the IOUT pin.

Figure 7-71. IOUT vs Compliance Headroom Voltage

Time (5 µs/div)

IOUT (4 mA/div)

LATCH (5 V/div)

C001

4 mA to 20 mA range

LOAD = 300 Ÿ

From code: 0000h

To code:

FFFFh

AVDD = +24 V

AVSS = 0 V

Figure 7-72. 4-mA to 20-mA Rising

Time (5 µs/div)

IOUT (4 mA/div)

LATCH (5 V/div)

C001

AVDD = +24 V

AVSS = 0 V

From code:FFFFh

To code:

0000h

4 mA to 20 mA range

LOAD = 300 Ÿ

Figure 7-73. 4-mA to 20-mA Falling

Time (60 µs/div)

C001

AVDD = 24 V

AVSS = 0 V

LOAD = 300 Ÿ

Figure 7-74. IOUT Power-On Glitch

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DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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