DAC8760IPWPR.B datasheet(46/69 Pages) TI2

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Controlling the VOUT and IOUT Pins

This section describes how to control the VOUT and IOUT pins for three use cases:

9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled

In most applications, VOUT and IOUT are not connected together. In addition, only one is enabled at a time or

they are both powered down. In this configuration, bits 10 down to 7 of the Configuration Register must be set to

0000 (default value). Bits 2 down to 0 of the Control Register (RANGE bits) control VOUT and IOUT.

9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled

When VOUT and IOUT are independent outputs and simultaneously enabled, bit 8 of the Configuration Register

(DUAL OUTEN) must be set to 1. Bits 2 down to 0 of the Control Register (RANGE bits) control VOUT and bits

10 down to 9 of the Configuration Register (IOUT RANGE) control IOUT. Note that only one DAC code register

exists and therefore the voltage and current outputs are controlled by the same code. Note that changing the

RANGE bits at any time causes the DAC data register to be cleared based on the value of the CLR-SEL pin or

CLRSEL register bit and the new value of the RANGE bits.

9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled

When the VOUT and IOUT pins are tied together, bit 8 of the Configuration Register (DUAL OUTEN) must be set

to 0. Bits 2 down to 0 of the Control Register (RANGE) control VOUT and IOUT. Special consideration must be

paid to the +VSENSE pin in this case. When VOUT is disabled, the +VSENSE pin is connected to the internal

amplifier input through an internal 60-kΩ resistor as shown in Figure 8-2. This internal node has diode clamps to

REFIN and GND. Setting bit 6 of the Configuration Register (APD) forces this internal node to be tied to GND

through a 10-kΩ resistor, in effect, the +VSENSE pin is tied to GND through a 70-kΩ power-down resistor. Figure

9-1 shows the leakage current into the +VSENSE pin for both settings of the APD bit.

-400

-300

-200

-100

100

200

300

-12

-8

-4

+VSENSE Pin Voltage (V)

APD bit disabled

APD bit enabled

C002

AVDD = +24 V

AVSS = -12 V

Output disabled

Figure 9-1. +VSENSE Leakage Current vs Pin Voltage

Whether the APD bit is set or not set, the current output in this case incurs a gain error because the internal

resistor acts as a parallel load in addition to the external load. If this gain error is undesirable, it can be corrected

through the gain calibration register shown in Table 8-20. Another option is to use the application circuit in Figure

9-2.

DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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