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DAC8760IPWPR.B Datasheet(PDF) 36 Page - Texas Instruments

Part # DAC8760IPWPR.B
Description  DACx760 Single-Channel, 12- and 16-Bit Programmable Current and Voltage Output Digital-to-Analog Converters for 4-mA to 20-mA Current-Loop Applications
PDF  69 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC8760IPWPR.B Datasheet(HTML) 36 Page - Texas Instruments

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The time required for the output to slew over a given range can be expressed as Equation 7:
Slew Time =
Output Change
Step Size Update Clock Frequency LSB Size
·
·
(7)
where
• Slew Time is expressed in seconds
• Output Change is expressed in amps (A) for IOUT or volts (V) for VOUT
When the slew rate control feature is enabled, all output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to
the zero-scale value at the programmed slew rate. To verify that the slew operation has completed, read Bit
1 (SR-ON) of the Status Register. The update clock frequency for any given value is the same for all output
ranges. The step size, however, varies across output ranges for a given value of step size because the LSB
size is different for each output range. Figure 8-5 illustrates an example of IOUT slewing at a rate set by the
previously described parameters. In this example for the DAC8760 (LSB size of 305 nA for the 0-mA to 20-mA
range), the settings correspond to an update clock frequency of 6.9 kHz and a step size of 128 LSB. As shown
for the case with no capacitors on CAP1 or CAP2, the steps occur at the update clock frequency (6.9 kHz
corresponds to a period close to 150 µs) and the size of each step is about 38 µA (128 × 305 nA). The slew time
for a specific code change can be calculated using Equation 7.
Time (150 µs/ div)
no cap
3 nF CAP1
3 nF CAP2
10 nF CAP1
10 nF CAP2
C001
0 mA to 20 mA range
SRCLK=1100h
SRSTEP = 111h
Figure 8-5. IOUT vs Time With Digital Slew Rate Control
Apply the desired programmable slew rate control setting prior to updating the DAC data register because
updates to the DAC data register in tandem with updates to the slew rate control registers can create race
conditions that may result in unexpected DAC data.
DAC7760, DAC8760
SBAS528D – JUNE 2013 – REVISED DECEMBER 2021
www.ti.com
36
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC7760 DAC8760



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