DAC8760IPWPR.B datasheet(31/69 Pages) TI2

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8.3.4 Internal Reference

The DACx760 includes an integrated 5-V reference with a buffered output (REFOUT) capable of driving up to

5 mA (source or sink) with an initial accuracy of ±5 mV (maximum) and a temperature drift coefficient of

10 ppm/°C (maximum).

8.3.5 Digital Power Supply

An internally generated 4.6-V supply capable of driving up to 10 mA can be output on DVDD by leaving the

DVD-EN pin unconnected. This configuration simplifies the system power-supply design especially when an

isolation barrier is required to cross and generate the digital supply. The internally generated supply can be used

to drive isolation components used for the digital data lines and other miscellaneous components like references

and temp sensors. See Figure 9-6 for an example application. If an external supply is preferred, the DVDD pin

(which can be driven up to 5.5 V in this case) can be made into an input by tying DVDD-EN to GND (see Section

7.5 for detailed specifications).

8.3.6 DAC Clear

The DAC has an asynchronous clear function through the CLR pin, which is active-high and allows the voltage

output to be cleared to either zero-scale code or midscale code. This action is user-selectable through the

CLR-SEL pin or the CLRSEL bit of Table 8-17, as Table 8-2 describes. The CLR-SEL pin and CLRSEL register

are ORed together. The current output clears to the bottom of its preprogrammed range. When the CLR signal

returns to low, the output remains at the cleared value. The pre-clear value can be restored by pulsing the

LATCH signal without clocking any data. A new value cannot be programmed until the CLR pin returns to low.

Note that in dual-output mode, the value that the DAC data register is cleared to follows the settings for the

voltage output mode.

Table 8-2. CLR-SEL Options

CLR-SEL

OUTPUT VALUE

UNIPOLAR OUTPUT RANGE

BIPOLAR OUTPUT RANGE

0 V

Midscale

Negative full-scale

In addition to defining the output value for a clear operation, the CLRSEL bit and the CLR-SEL pin also define

the default output value. During the selection of a new voltage range, the output value corresponds to the

definitions given in Table 8-7. To avoid glitches on the output, disable the output by writing a 0 to the OUTEN bit

of Table 8-17 before changing the voltage range. When the OUTEN bit is set to 1, the output goes to the default

value as defined by the CLRSEL bit and the CLR-SEL pin.

8.3.7 Power-On Reset

The DACx760 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD

POR signals are ANDed together so that both supplies must be at their minimal specified values for the device

to not be in a reset condition. These POR circuits initialize internal logic and registers as well as set the analog

outputs to a known state while the device supplies are ramping. All registers are reset to their default values with

the default value of the data register being determined by the CLR-SEL pin. The behavior of IOUT and VOUT is

described in their respective sections. Typically the POR function can be ignored as long as the device supplies

power up and maintain the specified minimum voltage levels. However, in the case of supply drop or brownout,

the DACx760 can have an internal POR reset event or lose digital memory integrity. Figure 8-4 represents the

threshold levels for the internal POR for both the DVDD and AVDD supplies.

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DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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