DAC8760IPWPR.B datasheet(44/69 Pages) TI2

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8.6.1.1.2 Configuration Register

The DACx760 configuration register is written to at address 0x57. Table 8-18 summarizes the description for the

configuration register bits.

Table 8-18. Configuration Register 0x57

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB11

Reserved. User must not write any value other than zero to these bits.

DB10:DB9

IOUT RANGE

IOUT range. These bits are only used if both voltage and current outputs

are simultaneously enabled through bit 8 (DUAL OUTEN). The voltage output

range is still controlled by bits 2:0 of the Control Register (RANGE bits).

The current range is controlled by these bits and has similar behavior to

RANGE[1:0] when RANGE[2] = 1. However, unlike the RANGE bits, a change

to this field does not make the DAC data register go to its default value.

DB8

DUAL OUTEN

DAC dual output enable. This bit controls if the voltage and current outputs are

enabled simultaneously. Both are enabled when this bit is high. However, both

outputs are controlled by the same DAC data register.

DB7

APD

Alternate power down. On power-up, +VSENSE is connected to the internal

VOUT amplifier inverting pin. Diodes exist at this node to REFIN and GND.

Setting this bit connects this node to ground through a resistor. When set, the

equivalent resistance seen from +VSENSE to GND is 70 kΩ. This is useful in

applications where the VOUT and IOUT pins are tied together.

DB6

Reserved. Do not write any value other than zero to these bits.

DB5

CALEN

User calibration enable. When user calibration is enabled, the DAC data are

adjusted according to the contents of the gain and zero calibration registers.

See Section 8.3.11.

DB4

HARTEN

Enable interface through HART-IN pin (only valid for IOUT set to 4-mA to

20-mA range through RANGE bits).

Bit = 1: HART signal is connected through internal resistor and modulates

output current.

Bit = 0: HART interface is disabled.

DB3

CRCEN

Enable frame error checking.

DB2

WDEN

Watchdog timer enable.

DB1:DB0

WDPD[1:0]

Watchdog timeout period.

8.6.1.1.3 DAC Registers

The DAC registers consist of a DAC data register (Table 8-19), a DAC gain calibration register (Table 8-20),

and a DAC zero calibration register (Table 8-21). User calibration as described in Section 8.3.11 is a feature

that allows for trimming the system gain and zero errors. Table 8-19 through Table 8-21 show the DAC8760,

16-bit version of these registers. The DAC7760 (12-bit version) register contents are located in DB15:DB4. For

DAC7760, DB3:DB0 are don't care bits when writing and zeros when reading.

Table 8-19. DAC Data Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

D15:D0

0000h

DAC data register. Format is unsigned straight binary.

Table 8-20. DAC Gain Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

G15:G0

0000h

Voltage and current gain calibration register for user calibration. Format is

unsigned straight binary.

Table 8-21. DAC Zero Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

Z15:Z0

0000h

Voltage and current zero calibration register for user calibration. Format is twos

complement.

DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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