DAC8760IPWPR.B datasheet(40/69 Pages) TI2

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8.5 Programming

8.5.1 Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates

at clock rates of up to 30 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP)

standards. The SPI communication command consists of a write address byte and a data word for a total of 24

bits. The timing for the digital interface is shown in Figure 7-1 and Figure 7-2.

8.5.1.1 SPI Shift Register

The default frame is 24 bits wide (see Section 8.3.10 for 32-bit frame mode) and begins with the rising edge of

SCLK that clocks in the MSB. The subsequent bits are latched on successive rising edges of SCLK. The default

24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 8-12.

Table 8-12. Default SPI Frame

BIT 23:BIT 16

BIT 15:BIT 0

Address byte

Data word

The host processor must issue 24 bits before it issues a rising edge on the LATCH pin. Input data bits are

clocked in regardless of the LATCH pin and are unconditionally latched on the rising edge of LATCH. By default,

the SPI shift register resets to 000000h at power on or after a reset.

8.5.1.2 Write Operation

A write operation is accomplished when the address byte is set according to Table 8-13. For more information on

the DACx760 registers, see Section 8.6.1.

Table 8-13. Write Address Functions

ADDRESS BYTE

FUNCTION

0x00

No operation (NOP)

0x01

Write DAC Data register

0x02

0x55

Write control register

0x56

Write reset register

0x57

Write configuration register

0x58

Write DAC gain calibration register

0x59

Write DAC zero calibration register

0x95

Watchdog timer reset

0x96

CRC error reset

8.5.1.3 Read Operation

A read operation is accomplished when the address byte is 0x02. Follow the read operation with a no-operation

(NOP) command to clock out an addressed register, as shown in Figure 7-2. To read from a register, the address

byte and data word is as shown in Table 8-14. The read register value is output MSB first on SDO on successive

falling edges of SCLK.

Table 8-14. Default SPI Frame for Register Read

ADDRESS BYTE

DATA WORD

BIT 15:BIT 6

BIT 5:BIT 0

0x02

X (don't care)

DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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