44
0832F–HIREL–02/07
PC7410
e2v semiconductors SAS 2007
When selecting which filter to use on the AV
DD input of the PC7410 CBGA device specifically, system
designers should refer to Erratum No. 18 in the PC7410 RISC Microprocessor Chip Errata
(MPC7410CE). The AV
DD input of the PC7410 CBGA device is sensitive to system noise on both the
V
DD power plane, as described above, and the OVDD power plane as described in the Erratum No. 18.
With these AV
DD sensitivities to OVDD and VDD noise, care must be taken when selecting the filter circuit
for the AV
DD input of the PC7410 CBGA device. Erratum No. 18 does not apply to the AVDD input of the
MPC7401 HCTE device, nor does it affect the L2AV
DD input of either the HCTE or the CBGA device.
As described in Erratum No. 18, when there is a high amount of noise on the OV
DD power plane due to
I/O switching rates, it is possible for the OV
DD noise to couple into the PLL supply voltage (AVDD) internal
to the PC7410 CBGA package. It is the recommendation of Freescale, that new designs using the
PC7410 CBGA package provide the ability to implement either filter shown in Figure 14-1 and Figure 14-
2 at the AV
DD input. Existing designs that implemented Figure 14-1 on AVDD may never experience the
error described in Erratum No. 18. Both new and existing designs should qualify both AV
DD filter solu-
tions, and the filter providing the most robust margin should be implemented.
Figure 14-1. PLL Power Supply Filter Circuit No.1
Figure 14-2. PLL Power Supply Filter Circuit No.2
The filter circuit should be placed as close as possible to the AV
DD pin to minimize noise coupled from
nearby circuits. A separate circuit should be placed as close as possible to the L2AV
DD pin. It is often
possible to route directly from the capacitors to the AV
DD pin, which is on the periphery of the 360 CBGA
footprint, without the inductance of vias. The L2AV
DD pin may be more difficult to route, but is proportion-
ately less critical.
It is the recommendation of Freescale, that systems that implement the AV
DD filter shown in Figure 14-2
design in the pads for the removed capacitors (shown in Figure 14-1), to provide for the possible reintro-
duction of the filter in Figure 14-1. This would be necessary in case there is a planned transition from the
CBGA package to the HiTCE package of the PC7410.
VDD
10
Ω
2.2
µF
2.2
µF
GND
AVDD (or L2AVDD)
Low ESL surface mount capacitor
VDD
AVDD
51
Ω
GND
Capacitor
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