5
0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
• Completion
– 8-entry completion buffer
– Instruction tracking and peak completion of two instructions per cycle
– Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction flow changes
• Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
– Fixed-point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical
– Fixed-point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
– Single-cycle arithmetic, shifts, rotates, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
• Three-stage Floating-point Unit and a 32-entry FPR File
– Support for IEEE-754 standard single- and double-precision floating-point arithmetic
– Three-cycle latency, one-cycle throughput (single or double precision)
– Hardware support for divide
– Hardware support for denormalized numbers
– Time deterministic non-IEEE mode
• System Unit
– Executes CR logical instructions and miscellaneous system instructions
– Special register transfer instructions
• AltiVec Unit
– Full 128-bit data paths
– Two dispatchable units: vector permute unit and vector ALU unit
– Contains its own 32-entry 128-bit Vector Register File (VRF) with six renames
– The vector ALU unit is further sub-divided into the Vector Simple Integer Unit (VSIU), the
Vector Complex Integer Unit (VCIU) and the Vector Floating-point Unit (VFPU)
– Fully pipelined
• Load/Store Unit
– One-cycle load or store cache access (byte, half-word, word, double-word)
– Two-cycle load latency with one-cycle throughput
– Effective address generation
– Hits under misses (multiple outstanding misses)
– Single-cycle unaligned access within double-word boundary
– Alignment, zero padding, sign extend for integer register file
– Floating-point internal format conversion (alignment, normalization)
– Sequencing for load/store multiples and string operations
– Store gathering
– Executes the cache and TLB instructions
– Big- and little-endian byte addressing supported
– Misaligned little-endian supported
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