RIVA128 datasheet(65/77 Pages) STMICROELECTRONICS

65 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

65/77

SERR_ENABLE is an enable bit for the SERR# driver.

0=Disables the SERR# driver

1=Enables the SERR# driver

R W 0

7:6

Reserved

R - 0

PALETTE_SNOOP indicates that VGA compatible devices should snoop their

palette registers.

0=Palette accesses treated like all other accesses

1=Enables special palette snooping behavior

R W 0

WRITE_AND_INVAL is an enable bit for using the Memory Write and Invali-

date command.

1=The RIVA 128 as bus master may generate the command

0=The Memory Write command must be used instead of Memory Write and

Invalidate

R W 0

Reserved

R - 0

BUS_MASTER indicates that the device can act as a master on the PCI bus.

0=Disables the RIVA 128 from generating PCI accesses

1=Allows the RIVA 128 to behave as a bus master

R W 0

MEMORY_SPACE indicates that the RIVA 128 will respond to memory space

accesses.

0=Device response disabled

1=Enables response to Memory space accesses. The device will decode and

respond to the 16MByte ranges as well as the default VGA memory range

when it is enabled. The VGA decode range may change based upon the

value in the VGA graphics Miscellaneous Register GR06, bits[3:2] and other

enable bits, see RIVA 128

Programming Reference Manual [2].

R W 0

IO_SPACE indicates that the device will respond to I/O space accesses. This

bit enables I/O space accesses for the VGA function as defined in the PCI

specification. These include 0x3B0 - 0x3BB, 0x3C0 - 0x3DF and their aliases.

R W 0

Bits

Function

R W I

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