RIVA128 datasheet(57/77 Pages) STMICROELECTRONICS

57 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

57/77

IN-CIRCUIT BOARD TESTING

The RIVA 128 has a number of features designed to support in-circuit board testing. These include:

• Dedicated test mode input and dual-function test mode select pins selecting the following modes:

- Pin float

- Parametric NAND tree

- All outputs driven high

- All outputs driven low

• Checksum test

• Test registers

12.1 TEST MODES

Primary test control is provided by the dedicated TESTMODE input pin. The RIVA 128 is in normal oper-

ating mode when this pin is deasserted. When TESTMODE is asserted, MP_AD[3:0] are reassigned as

TESTCTL[3:0] respectively. Test modes are selected asynchronously through a combination of the pin

states shown in Table 17.

Table 17.

Test mode selection and descriptions

12.2 CHECKSUM TEST

The RIVA 128 hardware checksum feature supports

testing of the entire pixel datapath at full video rates

from the framebuffer through to the DAC inputs. Each

of the three RGB colors can be tested to provide a

correlation between the intended and actual display.

Checksums are accumulated during active (un-

blanked) display. Note that the checksum mecha-

nism does not check the DAC outputs (i.e. what is

physically being displayed on the monitor).

For a given image (which can be a real application’s

image or a specially prepared test card), theoretical-

ly derived checksum values can be calculated for a

selected RGB color, which are then compared with

the RIVA 128 hardware checksum value. Alternative-

ly the checksum value from a known good chip can

be used as the reference.

Hardware checksum accumulation is not affected by

the horizontal and vertical synchronization wave-

forms or timings. Any discrepancy between the cal-

culated and RIVA 128 hardware accumulated check-

sum values therefore indicates a problem in the

device or system being tested. Details of program-

ming the RIVA 128 checksum are given in the RIVA

128

Programming Reference Manual [2].

Test mode

TESTCTL[3:0]

Description

Parametric

NAND tree

A single parametric NAND tree is provided to give a quiescent environ-

ment in which to test VIL and VIH without requiring core activity.

This capability is provided in the pads by chaining all I and I/O paths to-

gether via two input NAND gates. The chain begins with one input of the

first NAND gate tied to VDD while the other input is connected to the first

device pin on the NAND tree. The output of this gate then becomes the in-

put of the next NAND gate in the tree and so on until all pad input paths

have been connected. The final NAND gate output is connected to an out-

put-only pin whose normal functionality is disabled in NAND tree mode.

The NAND tree length is therefore equal to the number of I and I/O pins in

the RIVA 128. Output -only pins are not connected into the NAND tree.

Pin float

All pin output drivers are tristated in this test mode so that pin leakage

current (IIL,IIH,IOZL,IOZH) can be measured.

Outputs high

All pin output drivers drive a high output state in this test mode so that

output high voltage (VOH at IOH) can be measured.

Outputs low

All pin output drivers drive a low output state in this test mode so that out-

put low voltage (VOL at IOL) can be measured.

RIVA128 Datasheet(PDF) 57 Page - STMicroelectronics

RIVA128 Datasheet(HTML) 57 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL