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SABRE-LL-I Datasheet(PDF) 107 Page - STMicroelectronics |
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SABRE-LL-I Datasheet(HTML) 107 Page - STMicroelectronics |
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107 / 141 page ![]() SABRE-LL-I GPIO pins 107/141 22.7 GPIO[5] The GPIO[5] truth table is (for the abbreviation list please refer to Table 68): Figure 33. GPIO[5] block diagram Table 79. GPIO[5] truth Master(1) 1. Master bit is at logic level “1” when S.A.B.Re is used as a master device (seeChapter 8) AUX1 system and Vloop1 external(2) GPIO[5] SPI BITS Function Note GpioOut enable[5] Mode[2] Mode[1] Mode[0] 1 X X X X X Slave control 0 1 X X X X Reg Loop1 OUT (3) 0 0 0 X X X HiZ (SPI_IN) 0 0 1 000 SPI OUT (3) 0 0 1 001 Comp1OUT (3) 0 0 1 0 1 0 Reg Loop1 OUT (3) 0 0 1 011 AuxPwm3 (3) 0 0 1 100 SPI OUT inverted (3) 0 0 1 1 0 1 Comp1OUT inverted (3) 0 0 1 110 Reg Loop1 OUT inverted (3) 0 0 1 1 1 1 AuxPwm3 inverted (3) GPIO[5] Logic Decode From Control logic V3v3 To ADC To internal Logic & SPI Back to Back Driver V3v3 V3V3 |
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